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Demand for serial flash memory continues to soar as designers of digital TVs, DVDs, PCs, modems, printers and mobile consumer electronics devices view the memory as an increasingly attractive code execution alternative to parallel NOR flash. "We think the market will jump from about $560 million last year to more than $1 billion this year as conversion from parallel to serial begins moving up to the 16- and 32-Mbit devices," said Alan Niebel, CEO of Web-Feet Research (Monterey, Calif.).
Driving increased demand are the memory's multiple advantages in terms of lower pin count, reduced board space, lower power and reduced system cost. In a standard eight-pin SO package, flash memories using the standard serial peripheral interface (SPI) need up to 80 percent less board space than a parallel flash in a typical 32-pin or larger PLCC.
Just as important is a serial flash memory's impact on design complexity. Whereas a typical 32-Mbit parallel flash requires 21 address lines, 16 data lines and three control lines between the MCU or ASIC and the memory, a 32-Mbit serial flash requires just two data and two control lines. Controllers with higher pin counts require more board layers for signal routing, and the more pins the controller devotes to system memory, the fewer pins are available to deliver the processing power and memory bandwidth needed to support new features.
To meet growing demand, serial flash suppliers Atmel, Macronix, Numonyx, Silicon Storage Technology (SST), Spansion and Winbond are offering higher-density devices. Spansion last year announced a 128-Mbit SPI flash IC using its 90-nm MirrorBit technology. But analysts say the real move to new applications will come with the arrival of devices featuring multibit interfaces.
Most initial serial flash deployments have focused on execute-in-place (XiP) applications. To execute these programs directly from memory, designers use NOR flash, which can be addressed as individual words. But the performance limitations of the traditional, single-bit SPI interface have forced designers in many applications to couple SPI-based serial flash with shadow RAM (usually an SRAM) to support faster access.
To overcome this limitation, eliminate the cost of the SRAM and improve boot time, several vendors have introduced devices equipped with multibit interfaces. Last August, Winbond Electronics Corp. introduced what it said was the first quad-SPI serial flash memory IC. The 16-Mbit memory, the first in a family of devices that will range up to 64 Mbits, offers single, dual and quad I/Os in a compact, eight-pin SOP. Supporting clock rates to 80 MHz, the device enables equivalent clock frequencies up to 320 MHz in quad-SPI mode, or more than six times the transfer rate of a standard serial flash memory running at 50 MHz. Random access overhead is cut by more than 70 percent by shrinking the number of clocks needed per read instruction from 40 to 12. Winbond claims that in a typical instruction fetch of 32 bytes, the quad device is capable of access rates of better than 32 Mbytes/s--roughly 50 percent better than a comparable parallel flash with 70-ns access and 100-ns cycle times.
Macronix has also expanded into multi-I/O serial flash with both dual and quad devices. In a conventional serial flash device, command and data are written into memory via the serial input (SI) pin. The Macronix dual I/O devices double the conventional data rate by changing the SI and serial out (SO) pins from single unidirectional data flow into multiple bidirectional flows. The company's quad-I/O devices extend the concept by converting the write protect (WP#) and hold (NC) pins to bidirectional as well. In quad-I/O mode, the data-out speed of the Macronix serial flash is said to surpass that of parallel flash when the code length of data or programming is longer than 4 bytes.
The 40 clock cycles needed by traditional single-I/O serial flash for specifying addresses include eight cycles for rewriting the read command, 24 cycles for address allocation and eight dummy cycles. The Macronix multi-I/O devices reportedly can save up to 20 clock cycles with a feature that eliminates the need to repeat cycles used for commands when random addresses are used.
The latest quad serial flash comes from SST. The company's engineers argue that although the existing multibit interfaces boost performance, they still rely on some artifacts of the original SPI architecture (such as a cumbersome single-bit command structure and extra commands for power management and lookahead functions) that hide performance latencies. SST has developed an architecture, called serial quad interface (SQI), that uses a 4-bit multiplexed serial communications protocol to boost code execution flexibility, in order to accelerate write and erase and improve low-power operation. Though the architecture still relies on SPI-like serial commands to support SPI protocols for read, high-speed read and Jedec ID read, these new capabilities support sustained burst data rates up to 350 Mbits/s.
Unlike traditional memories, the SST approach uses a zero-latency nibblewide architecture that enables true random access by allowing reads to start anywhere and to continue beyond boundaries as a page, block or plane without counting clocks. It also shrinks access time by supporting 8-, 16-, 32- and 64-byte burst-mode operation with a wraparound feature that lets designers execute code in burst snippets for RAMless applications, or to fill cache line buffers when the system architecture uses pipelining. Read memory index jumping reduces input clock cycles by letting the system jump from one address to another within a 256-byte page or a 64-kbyte block, or from block to block using indirect addressing. |